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19-2566; Rev 0; 8/02
MAX1198 Evaluation Kit
General Description
The MAX1198 evaluation kit (EV kit) is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX1195-MAX1198 dual 8-bit analog-to-digital converters (ADCs). The MAX1195-MAX1198 accept differential or single-ended analog inputs and the EV kit allows for evaluation of each ADC with both types of inputs from one single-ended analog signal. The digital output produced by the ADC can be easily sampled with a userprovided high-speed logic analyzer or data-acquisition system. The EV kit operates from 3.3V and 2.5V (MAX1198) power supplies. It includes circuitry that generates a clock signal from an AC signal provided by the user. The EV kit comes with the MAX1198 installed. Order free samples of the pin-compatible MAX1195, MAX1196, or MAX1197 to evaluate these parts.
Features
o Up to 100Msps Sampling Rate with MAX1198 o Low-Voltage and Low-Power Operation o Single-Ended or Fully Differential Signal Input Configuration o Clock-Shaping Circuit o Fully Assembled and Tested o Supports Both Nonmultiplexed (MAX1195, MAX1197, MAX1198) and Multiplexed (MAX1196) Output Operation
Evaluates: MAX1195-MAX1198
Ordering Information
PART TEMP RANGE 0C to +70C IC PACKAGE 48 TQFP-EP** MAX1198EVKIT
Selector Guide
PART MAX1198ECM MAX1197ECM MAX1195ECM MAX1196ECM* SPEED (Msps) 100 60 40 40, multiplexed output
**EP = Exposed paddle. Note: To evaluate the MAX1195/MAX1196/MAX1197, request a free sample with the MAX1198 EV kit.
*Future product--contact factory for availability.
Component List
DESIGNATION C1-C5, C7, C9, C11, C16-C19, C21, C23, C27, C31, C33, C34, C36-C39, C42-C49, C51, C52 C6, C50 C8, C10, C20, C22, C26, C32, C35, C40, C41 QTY DESCRIPTION 0.1F 10%, 16V ceramic capacitors (0603) Taiyo Yuden EMK107BJ104KA or TDK C1608X7R1C104KT Not installed (0603) 2.2F 10%, 10V tantalum capacitors (A case) AVX TAJA225K010R or Kemet T494A225K010AS 10F 20%, 10V tantalum capacitors (B case) AVX TAJB106M010 or Kemet T494B106K010AS 22pF 5%, 50V ceramic capacitors (0603) Murata GRM39COHG220J050AD or TDK C1608COG1H220JT DESIGNATION QTY DESCRIPTION 1000pF 10%, 50V ceramic capacitor (0603) TDK C1608X7R1H102KT or Murata GRM39X7R102K050AD 2 x 25-pin header 3-pin headers Ferrite chip beads, 90 at 100MHz (1206) Fair-Rite Products Corp. 2512069007Y0
32
C30
1
J1 0 JU1-JU8
1 8
9
L1, L2
2
C12-C15
4
R1, R6, R19, R29, R30, R49, R59, R60, R69 R2-R5, R35, R51-R58, R61-R68, R70, R71 R7
0
Not installed (0603)
C24, C25, C28, C29
26 1
49.9 1% resistors (0603) 0 5% resistor (0603)
4
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MAX1198 Evaluation Kit Evaluates: MAX1195-MAX1198
Component List (continued)
DESIGNATION R8, R21-R28, R41-R48, R50 R9, R10, R13, R14, R36 R11 R12, R37 R15-R18 R20 R31, R32, R33 R34 R38 S/E_INA, D/E_INA, S/E_INB, D/E_INB, CLOCK T1, T2 U1 QTY 21 5 1 2 4 1 0 1 1 5 DESCRIPTION 100 1% resistors (0603) 2k 1% resistors (0603) 6.04k 1% resistor (0603) 4.02k 1% resistors (0603) 24.9 1% resistors (0603) 10k 1% resistor (0603) Not installed (0805) 5k 12-turn potentiometer 3.9 5% resistor (0805) SMA PC-mount connectors RF transformers Mini-Circuits TT1-6-KK81 MAX1198ECM (48-pin TQFP-EP) Dual CMOS differential line receiver (8-pin SO) MAX9113ESA Buffers/drivers 3-state output (48-pin TSSOP) Texas Instruments SN74ALVCH16244DGG or Pericom PI74ALVCH16244A Shunts (JU1-JU8) MAX1198 EV kit PC board MAX1198 data sheet MAX1198 EV kit data sheet
* *
Analog bandpass filters (e.g., TTE elliptical function bandpass filter Q56 series) Digital voltmeter
Procedure
The MAX1198 EV kit is a fully assembled and tested surface-mount board. Follow the steps below for board operation. Do not turn on power supplies or enable function generators until all connections are completed. 1) Verify that shunts are installed across pins 2 and 3 of jumpers JU5 (offset binary digital output), JU6 (normal operation), JU7 (MAX1198 enabled), and JU8 (outputs enabled). 2) Connect the clock function generator to the CLOCK SMA connector. 3) Connect the output of the analog signal function generator to the input of the bandpass filter. 4) a) To evaluate differential analog signals on channel A, verify that shunts are installed on pins 2 and 3 of jumpers JU1 and JU2. Connect the output of the analog bandpass filter to the D/E_INA SMA connector. For single-ended analog signal evaluation on channel A, verify that shunts are installed on pins 1 and 2 of jumpers JU1 and JU2, and connect the output of the bandpass filter to the S/E_INA SMA connector. b) To evaluate differential analog signals on channel B, verify that shunts are installed on pins 2 and 3 of jumpers JU3 and JU4. Connect the output of the analog bandpass filter to the D/E_INB SMA connector. For single-ended analog signal evaluation on channel B, verify that shunts are installed on pins 1 and 2 of jumpers JU3 and JU4, and connect the output of the bandpass filter to the S/E_INB SMA connector. Note: Both channels can be operated independently or simultaneously. 5) Connect the logic analyzer to the header (J1). For nonmultiplexed output operation, channel A (channel B) data is captured on J1-1 (J1-27) through J115 (J1-41). If evaluating the multiplexed outputs of the MAX1196, channel A and channel B data is captured on a single 8-bit bus (J1-1 through J1-15) and the A/B indicator signal can be monitored on J1-23 (see Table 4 for bit locations and J1 header designations). The system clock for both multiplexed and nonmultiplexed output operation is available on pin J1-43. 6) Connect a 3.3V, 200mA power supply to VA and VADUT. Connect the ground terminal of this supply to AGND.
2 1
U2
1
U3, U4
2
None None None None
8 1 1 1
Quick Start
Recommended Equipment
* DC power supplies a) Digital: 2.5V, 100mA b) Analog: 3.3V, 200mA Function generator with low-phase noise and low jitter for clock input (e.g., HP8662A) Function generators for analog signal inputs (e.g., HP8662A) Logic analyzer or data-acquisition system (e.g., HP1663EP, HP16500C)
* * *
2
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MAX1198 Evaluation Kit
Component Suppliers
SUPPLIER AVX Fair-Rite Products Kemet Mini-Circuits Pericom Taiyo Yuden TDK Texas Instruments PHONE 843-946-0238 845-895-2055 864-963-6300 718-934-4500 800-435-2336 800-348-2496 847-803-6100 972-644-5580 FAX 843-626-3123 845-895-2629 864-963-6322 718-332-4661 408-435-0800 847-925-0899 847-390-4405 214-480-7800 WEBSITE www.avxcorp.com www.fair-rite.com www.kemet.com www.minicircuits.com www.pericom.com www.t-yuden.com www.component.tdk.com www.ti.com
Evaluates: MAX1195-MAX1198
Note: Please indicate that you are using the MAX1198 when contacting these component suppliers.
7) Connect a 2.5V, 100mA power supply to VD and VDDUT. Connect the ground terminal of this supply to DGND. 8) Turn on both power supplies. 9) With a voltmeter, verify that 1.32V is measured across test points TP1 and TP2. If the voltage is not 1.32V, adjust potentiometer R34 until 1.32V is obtained. 10) Enable the function generators. Set the clock function generator for an output amplitude of 2.4VP-P and clock frequency 100MHz. Set the analog input signal generators for an output amplitude 2VP-P and to the desired input frequency. The two function generators should be phase-locked to each other. 11) For nonmultiplexed output operation, set the logic analyzer to capture on the clock's rising edge. In multiplexed output operation mode, channel A data is presented on the falling edge and channel B data is presented on the rising edge of the logic analyzer clock. 12) Enable the logic analyzer. 13) Collect data using the logic analyzer.
specified below), the ADC can be evaluated with both types of inputs by supplying only one single-ended analog signal to the EV kit. The EV kit was designed as a four-layer PC board to optimize the performance of the MAX1198. Separate analog and digital power planes minimize noise coupling between analog and digital signals. For simple operation, the EV kit is specified to have 3.3V and 2.5V power supplies applied to analog and digital power planes, respectively. However, the digital plane can be operated down to 1.7V without compromising performance. The logic analyzer's threshold must be adjusted accordingly. Access to the outputs, channel A and channel B, is provided through connector J1. The 50-pin connector easily interfaces directly with a user-provided logic analyzer or data-acquisition system.
Power Supplies
The MAX1198 EV kit requires separate analog and digital power supplies for best performance. A 3.3V power supply is used to power the analog portion of the MAX1198 and the clock signal circuit. The MAX1198 analog supply voltage has a range of 2.7V to 3.6V; however, 3.3V must be supplied to the EV kit (VADUT, VA) to meet the minimum input voltage supply to the clock shaping circuit. A separate 2.5V power supply is used to power the digital portion (VDDUT, VD) of the MAX1198 and the buffer/driver; however, it operates with a voltage supply as low as 1.7V and as high as 3.6V. Enhanced dynamic performance is achieved when the digital supply voltage is lower than the analog supply voltage.
Detailed Description
The MAX1198 EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX1195-MAX1198, dual 8-bit ADCs. The MAX1195, MAX1197, and MAX1198 are dual-output, nonmultiplexed ADCs, where data is captured on two separate 8-bit bus lines. The MAX1196 provides digitized data of the two input channels in multiplexed fashion on a single 8-bit bus. The EV kit comes with the MAX1198, which can be evaluated with a maximum clock frequency of 100MHz. The MAX1198 accepts differential or single-ended analog input signals. With the proper board configuration (as
Clock
An on-board clock-shaping circuit generates a clock signal from a sine-wave signal applied to the CLOCK SMA connector. The input signal should not exceed an
3
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MAX1198 Evaluation Kit Evaluates: MAX1195-MAX1198
amplitude of 2.6V P-P . The frequency of the signal should not exceed 100MHz for the MAX1198. The clock frequency of the sinusoidal input signal determines the sampling frequency of the ADC. A differential line receiver (U2) processes the input signal to generate the CMOS clock signal. The signal's duty cycle can be adjusted with potentiometer R34. A clock signal with a 50% duty cycle (recommended) can be achieved by adjusting R34 until 1.32V (40% of the analog power supply) is produced across test points TP1 and TP2 when the analog voltage supply is set to 3.3V. The clock signal is available at the J1-43 pin (CK), which can be used as a clock source to the logic analyzer. JU7 controls full power-down mode, and jumper JU8 controls the outputs enable/disable mode. See Table 2 for jumper settings.
Reference Voltage
The MAX1198 requires an input voltage reference at the REFIN pin to set the full-scale analog signal voltage input. The stable on-chip voltage reference of 2.048V can be accessed at REFOUT. The EV kit was designed to use the on-chip voltage reference by connecting REFIN to REFOUT through resistor R20. The user can externally adjust the reference level, and hence the full-scale range, by installing a resistor at the R19 pad (located on the board's component side). The adjusted reference level can be calculated by applying the following equation: VREFIN = R19 x VREFOUT R19 + R20
Input Signal
The MAX1198 accepts differential or single-ended analog input signals applied to channels A or B. However, the EV kit requires only single-ended analog input signals, with an amplitude of less than 2VP-P provided by the user. During single-ended operation, the signal is applied directly to the ADC, while in differential mode, an onboard transformer converts the single-ended analog input to a differential analog signal for the ADCs differential input pins. To evaluate single-ended performance, connect the input signal to the S/E_INA (channel A) or S/E_INB (channel B) SMA connectors. To evaluate differential performance, connect the input signal to the D/E_INA (channel A) or D/E_INB (channel B) SMA connectors. For single-ended or differential operation, see Table 1 for jumper configuration. Note: When a differential signal is applied to the ADC, positive and negative input pins receive half of the supplied input signal, with an offset voltage of VADUT/2.
where R19 is the value of the resistor installed, R20 is a 10k resistor, and VREFOUT is 2.048V. Alternatively, the user can apply a stable, low-noise, external voltage reference directly at the REFIN pad to set the full-scale range.
Digital Output Format
The MAX1198 features two 8-bit, parallel, CMOS-compatible, digital outputs (channels A and B). The digital output coding can be chosen to be either in two's complement format or straight offset binary format by configuring jumper JU5. See Table 3 for jumper configuration. Two drivers buffer the ADC's channel A and B digital outputs. Each buffer is able to drive large capacitive loads, which can be present at the logic analyzer connection, without compromising the digital output signal. The outputs of the buffers are connected to a 50-pin header (J1) located on the right side of the EV kit, where the user can connect a logic analyzer or data-acquisition system. See Table 4 for channel and bit location on header J1.
Enable/Power-Down/Sleep Modes
The MAX1198 EV kit also features jumpers that allow the user to enable or disable functions of the data converter. Jumper JU6 controls the sleep mode, jumper
Table 1. Single-Ended/Differential Operation Jumper Configuration
JUMPER SHUNT POSITION 1 and 2 JU1, JU2 2 and 3 PIN CONNECTION INA+ pin connected to SMA connector S/E_INA and INA- pin connected to COM pin INA+ and INA- pins connected to transformer T1 INB+ pin connected to SMA connector S/E_INB and INB- pin connected to COM pin INB+ and INB- pins connected to transformer T2 EV KIT OPERATION Analog input signal is applied to channel A as a single-ended input. Analog input signal is applied to channel A as a differential input. Analog input signal is applied to channel B as a single-ended input. Analog input signal is applied to channel B as a differential input.
1 and 2 JU3, JU4 2 and 3
4
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MAX1198 Evaluation Kit Evaluates: MAX1195-MAX1198
Table 2. Output Enable/Power-Down/Sleep-Mode Configuration
JUMPER JU6 SHUNT POSITION 1 and 2 2 and 3 1 and 2 2 and 3 1 and 2 2 and 3 PIN CONNECTION SLEEP connected to VDDUT SLEEP connected to DGND PD connected to VDDUT PD connected to DGND OE connected to VDDUT OE connected to DGND EV KIT OPERATION MAX1198 is disabled except for the internal reference. MAX1198 in normal operation mode. MAX1198 is powered down. MAX1198 in normal operation mode. Digital outputs disabled. Digital outputs enabled.
JU7 JU8
Table 3. Output Format
JUMPER JU5 SHUNT POSITION 1 and 2 2 and 3 MAX1198 T/B PIN Connected to VDDUT Connected to DGND OPERATION Digital output in two's complement Digital output in straight offset binary
Table 4. Output Bit Location (Nonmultiplexed/Multiplexed Output Operation)
CHANNEL A CLK B CLK A CLK B CLK A/B STATE BIT D0 J1-15 A0 J1-27 B0 BIT D1 J1-13 A1 J1-29 B1 BIT D2 J1-11 A2 J1-31 B2 BIT D3 J1-9 A3 J1-33 B3 BIT D4 J1-7 A4 J1-35 B4 BIT D5 J1-5 A5 J1-37 B5 BIT D6 J1-3 A6 J1-39 B6 BIT D7 J1-1 A7 J1-41 B7 NONMULTIPLEXED OUTPUT OPERATION N/A N/A
MULTIPLEXED OUTPUT OPERATION* 1 0 J1-15 A0 J1-15 A0 J1-13 A1 J1-13 A1 J1-11 A2 J1-11 A2 J1-9 A3 J1-9 A3 J1-7 A4 J1-7 A4 J1-5 A5 J1-5 A5 J1-3 A6 J1-3 A6 J1-1 A7 J1-1 A7
*Leave pins J1-27 to J1-41 (designated by B0-B7) unconnected. Monitor the A/B indicator signal on (J1-23).
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5
Evaluates: MAX1195-MAX1198
VD REFIN C19 0.1F REFIN VDDUT VD C14 10F 10V
MAX1198 Evaluation Kit
Figure 1. MAX1198 EV Kit Schematic (Sheet 1 of 2)
C18 0.1F S/E_B R13 2k 1% D7A C8 2.2F 10V C10 2.2F 10V 48 REFN REFOUT N.C. 36 N.C. 35 OGND 34 OVDD 33 5 INAL2 VDDUT FERRITE C37 0.1F OVDD 32 OGND 31 6V DD C38 0.1F C39 0.1F R30 OPEN R29 OPEN D7A D6A D5A D4A D3A D2A D1A D0A COM VADUT C23 0.1F 2 GND 4 INA+ C22 2.2F 10V 2V DD C20 2.2F 10V C21 0.1F 1 COM REFP REFIN 47 46 C11 0.1F R20 10k 1% 45 R21 100 1% 44 R22 100 1% 43 R23 100 1% 42 R24 100 1% 41 R25 100 1% 40 R26 100 1% 39 R27 100 1% 38 R28 100 1% 37 C9 0.1F D6A D5A D4A D3A D2A D1A D0A C6 OPEN C7 0.1F C1 0.1F C13 10F 10V R9 2k 1% REFIN R19 OPEN R1 OPEN R10 2k 1% S/E_B R14 2k 1% 3 COM 2 1 VADUT COM 1 JU3 2 3 7 GND 8 INBC26 2.2F 10V C27 0.1F C51 0.1F R16 C25 24.9 22pF 1% 1 JU2 2 3 1 JU1 2 3 R15 C24 24.9 22pF 1%
6
U1 MAX1198
N.C. 30 (A/B)* N.C. 29 C40 2.2F 10V R50 100 1% A/B R49 OPEN 3 2 COM 1% 9 INB+ 10 GND D1B 27 11 V DD D2B 26 1 C52 0.1F R17 C28 24.9 22pF D0B 28 R48 100 1% D0B R47 100 1% VADUT R18 C29 24.9 22pF 1% 3 JU4 2 1 C34 0.1F D1B R46 100 1% R45 100 1% D3B 25 VDD 14 VADUT VDD 15 GND 16 VDDUT 1 23 JU5 C31 0.1F 1 RIN1U2 MAX9113 ROUT1 ROUT2 GND 5 R8 100 1% 6 1A1 7 R7 0 RIN2RIN1+ RIN2+ VCC VA 4 2 3 C5 0.1F R12 4.02k 1% 8 TP2 C36 0.1F VDDUT 1 R31 OPEN 23 JU6 VDDUT 1 R32 OPEN R33 OPEN R38 3.9 23 JU7 VDDUT 1 23 JU8 *PIN A/B IS APPLICABLE TO THE MAX1196 ONLY D7B D6B D5B D4B R41 100 1% R42 100 1% R43 100 1% R44 100 1% T/B 17 SLEEP 18 PD 19 OE 20 D7B 21 D6B 22 D5B 23 D4B 24 D2B 12 CLK GND 13 D3B C32 2.2F 10V C30 1000pF C33 0.1F TP1 C35 2.2F 10V R11 6.04k 1%
VA
VA
AGND
C16 0.1F
C15 10F 10V
VADUT
DGND
VADUT
VDDUT
C17 0.1F
C12 10F 10V
S/E_INA
R2 49.9 1%
D/E_INA
C2 0.1F
4
T1
5
R3 49.9 1%
6
4
T2
D/E_INB
C3 0.1F
5
6
R4 49.9 1%
S/E_INB
C4 0.1F
S/E_B
R5 49.9 1%
R6 OPEN
VA
R37 4.02k 1%
1
R34 5k
2
3
_______________________________________________________________________________________
R36 2k 1%
CLOCK
R35 49.9 1%
MAX1198 Evaluation Kit Evaluates: MAX1195-MAX1198
U3 SN74ALVCH16244 1 2 3 4 5 6 7 C48 0.1F 8 9 10 R60 OPEN J1-19 R59 OPEN J1-17 R58 49.9 1% J1-15 R57 49.9 1% J1-13 R56 49.9 1% J1-11 R55 49.9 1% VDB J1-9 11 10E 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 20E 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 48 47 46 45 44 43 42 41 40 39 38 R61 49.9 1% J1-41 R62 49.9 1% J1-39 36 R63 49.9 1% J1-37 R64 49.9 1% J1-35 R65 49.9 1% D2A J1-33 R66 49.9 1% VDB J1-31 C44 0.1F C43 0.1F VDB L1 FERRITE C41 2.2F 10V VD J1-43 3 4 5 6 7 8 9 10 11 R71 49.9 1% 1 2
U4 SN74ALVCH16244 10E 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 20E 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 48 47 46 45 44 43 VDB 42 41 40 39 38 C47 0.1F C50 OPEN
J1-2 J1-4 1A1 J1-6 J1-8 J1-10 J1-12 J1-14 J1-16 J1-18 J1-20 J1-21 J1-22 J1-24
VDB
VDB
VDB
D7B
12
2Y4
2A4
37
12
2Y4
2A4
37
D6B
J1-26 J1-28
13
3Y1
3A1
D0A
13
3Y1
3A1
36
D5B
J1-30 J1-32
14 15 16
3Y2 GND 3Y3
3A2 GND 3A3
35 34 33
D1A
14 15 16
3Y2 GND 3Y3
3A2 GND 3A3
35 34 33
D4B J1-34 J1-36 D3B J1-38
17 18
3Y4 VCC
3A4 VCC
32 31
D3A
VDB
17 18
3Y4 VCC
3A4 VCC
32 31
D2B VDB
J1-40 J1-42 C46 0.1F J1-44 J1-45 J1-46
C45 0.1F J1-7
R54 49.9 1% R53 49.9 1%
C42 0.1F 30 D4A
C49 0.1F J1-29
19
R67 49.9 1% R68 49.9 1%
4Y1
4A1
19
4Y1
4A1
30
D1B
J1-5 R52 49.9 1% J1-3 R51 49.9 1% J1-1
20 21 22
4Y2 GND 4Y3
4A2 GND 4A3
29 28 27
D5A
J1-27 R69 OPEN
20 21 22
4Y2 GND 4Y3
4A2 GND 4A3
29 28 27
D0B J1-47 J1-48 J1-49
D6A
J1-25 R70 49.9 1%
23 24
4Y4 40E
4A4 30E
26 25
D7A
J1-23
23 24
4Y4 40E
4A4 30E
26 25
A/B
J1-50
Figure 1. MAX1198 EV Kit Schematic (Sheet 2 of 2)
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7
MAX1198 Evaluation Kit Evaluates: MAX1195-MAX1198
1.0"
1.0"
Figure 2. MAX1198 EV Kit Component Placement Guide-- Component Side
Figure 3. MAX1198 EV Kit PC Board Layout--Component Side
8
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MAX1198 Evaluation Kit Evaluates: MAX1195-MAX1198
1.0"
1.0"
Figure 4. MAX1198 EV Kit PC Board Layout--Ground Planes
Figure 5. MAX1198 EV Kit PC Board Layout--Power Planes
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9
MAX1198 Evaluation Kit Evaluates: MAX1195-MAX1198
1.0"
1.0"
Figure 6. MAX1198 EV Kit PC Board Layout--Solder Side
Figure 7. MAX1198 EV Kit Component Placement Guide-- Solder Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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